1. Field of the Invention
The present invention relates to a layout pattern verification system for verifying the electrical property of a layout pattern forming a prescribed logic circuit.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional layout pattern verification system for a logic circuit. As shown in the figure, circuit connection data D1 of a logic circuit corresponding to a layout pattern to be subjected to layout verification are taken in circuit constant extraction means 1, while data D2 of the layout pattern to be subjected to layout verification are taken in another circuit constant extraction means 2. When the object of layout pattern verification is transistor size, for example, channel length L1 and channel width W1 of a transistor 10 are taken in the circuit constant extraction means 1 from circuit connection data D1 typically shown in FIG. 2, while channel length L2 and channel width W2 are taken in the circuit constant extraction means 2 from layout pattern data D2 typically shown in FIG. 3. Referring to FIG. 3, numeral 11 denotes a diffusion region and numeral 12 denotes a polysilicon region, and an overlapping part of these regions 11 and 12 serves as a transistor (gate) forming region 13 of the transistor 10.
Circuit constants (L1, W1, L2 and W2 in the example shown in FIGS. 2 and 3) obtained by the extraction means 1 and 2 are taken in a verification part 3. The verification part 3 compares verification data obtained from the circuit constant extraction means 1 with verification data obtained from the circuit constant extraction means 2, thereby to verify whether or not the layout pattern is correctly designed. When an error is determined, it outputs an error list EL describing a designation specifying the transistor, a gain coefficient ratio and the like. In the example shown in FIGS. 2 and 3, the layout pattern is verified by comparing the channel length L1 and the channel width W1 with the channel length L2 and the channel width W2 respectively. If L1=L2 and W1=W2, it is determined that the layout pattern is correctly designed. If L1.noteq.L2 or W1.noteq.W2, on the other hand, the error list EL is outputted. When the error list EL is thus outputted, the designer can correct the layout pattern with reference to the error list EL, thereby to change the layout pattern data D2 in order to implement an intended circuit.
The conventional layout pattern verification system for a logic circuit having the aforementioned structure merely verifies dimensional characteristics, such as the transistor size, of an element forming a logic circuit.
In order to also guarantee the electrical property of the logic circuit in the designed layout pattern, it is necessary to separately execute circuit simulation on the basis of the circuit connection data D1.
However, if the logic circuit to be verified has large scale circuit structure, it is extremely unrealistic to carry out circuit simulation. To this end, it is impossible to guarantee the electrical property of the logic circuit in the layout pattern verification system under the present circumstances.
Further, it is necessary to change dimensional characteristics such as the transistor size (channel length and channel width) with respect to the circuit connection data D1 at any time following refinement of aluminum interconnection, formation width of a polysilicon layer and the like as cell as change in design rule of a wafer process due to technical development etc.